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<div class="header">
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<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">Interrupt Masks<div class="ingroups"><a class="el" href="group__group__dmac.html">DMAC         (Direct Memory Access Controller)</a><a class="el" href="group__group__dmac.html">DMAC         (Direct Memory Access Controller)</a> &raquo;  &#124; <a class="el" href="group__group__dmac__macros.html">Macros</a></div></div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gafdba1f920225bf6f028437646a5613a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#gafdba1f920225bf6f028437646a5613a0">CY_DMAC_INTR_COMPLETION</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_COMPLETION_Msk)</td></tr>
<tr class="memdesc:gafdba1f920225bf6f028437646a5613a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting.  <a href="#gafdba1f920225bf6f028437646a5613a0">More...</a><br /></td></tr>
<tr class="separator:gafdba1f920225bf6f028437646a5613a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d9872aeff6bb7b117c36ea4410df912"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#ga3d9872aeff6bb7b117c36ea4410df912">CY_DMAC_INTR_SRC_BUS_ERROR</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:ga3d9872aeff6bb7b117c36ea4410df912"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 1: Bus error for a load from the source.  <a href="#ga3d9872aeff6bb7b117c36ea4410df912">More...</a><br /></td></tr>
<tr class="separator:ga3d9872aeff6bb7b117c36ea4410df912"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92e5404a2d5c9d5062641bd421c84829"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#ga92e5404a2d5c9d5062641bd421c84829">CY_DMAC_INTR_DST_BUS_ERROR</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:ga92e5404a2d5c9d5062641bd421c84829"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 2: Bus error for a store to the destination.  <a href="#ga92e5404a2d5c9d5062641bd421c84829">More...</a><br /></td></tr>
<tr class="separator:ga92e5404a2d5c9d5062641bd421c84829"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfac4a721243f6224de04c57fbeaaf6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#gacfac4a721243f6224de04c57fbeaaf6a">CY_DMAC_INTR_SRC_MISAL</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_SRC_MISAL_Msk)</td></tr>
<tr class="memdesc:gacfac4a721243f6224de04c57fbeaaf6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 3: Misalignment of the source address.  <a href="#gacfac4a721243f6224de04c57fbeaaf6a">More...</a><br /></td></tr>
<tr class="separator:gacfac4a721243f6224de04c57fbeaaf6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a4463389bb1c3e079456022a30d9c41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#ga8a4463389bb1c3e079456022a30d9c41">CY_DMAC_INTR_DST_MISAL</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_DST_MISAL_Msk)</td></tr>
<tr class="memdesc:ga8a4463389bb1c3e079456022a30d9c41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 4: Misalignment of the destination address.  <a href="#ga8a4463389bb1c3e079456022a30d9c41">More...</a><br /></td></tr>
<tr class="separator:ga8a4463389bb1c3e079456022a30d9c41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39b68dc568f3f671eb28d8f52e480538"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#ga39b68dc568f3f671eb28d8f52e480538">CY_DMAC_INTR_CURR_PTR_NULL</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk)</td></tr>
<tr class="memdesc:ga39b68dc568f3f671eb28d8f52e480538"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 5: The channel is enabled and the current descriptor pointer is "0".  <a href="#ga39b68dc568f3f671eb28d8f52e480538">More...</a><br /></td></tr>
<tr class="separator:ga39b68dc568f3f671eb28d8f52e480538"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab33ccbb9279592dcc8bedbf77569ddbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#gab33ccbb9279592dcc8bedbf77569ddbb">CY_DMAC_INTR_ACTIVE_CH_DISABLED</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk)</td></tr>
<tr class="memdesc:gab33ccbb9279592dcc8bedbf77569ddbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 6: The channel is disabled and the data transfer engine is busy.  <a href="#gab33ccbb9279592dcc8bedbf77569ddbb">More...</a><br /></td></tr>
<tr class="separator:gab33ccbb9279592dcc8bedbf77569ddbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf018a967f58d71bb541b31690276d835"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__dmac__macros__interrupt__masks.html#gaf018a967f58d71bb541b31690276d835">CY_DMAC_INTR_DESCR_BUS_ERROR</a>&#160;&#160;&#160;(DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk)</td></tr>
<tr class="memdesc:gaf018a967f58d71bb541b31690276d835"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit 7: Bus error for a load of the descriptor.  <a href="#gaf018a967f58d71bb541b31690276d835">More...</a><br /></td></tr>
<tr class="separator:gaf018a967f58d71bb541b31690276d835"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gafdba1f920225bf6f028437646a5613a0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafdba1f920225bf6f028437646a5613a0">&#9670;&nbsp;</a></span>CY_DMAC_INTR_COMPLETION</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_COMPLETION&#160;&#160;&#160;(DMAC_CH_V2_INTR_COMPLETION_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 0: Completion of data transfer(s) as specified by the descriptor's interruptType setting. </p>

</div>
</div>
<a id="ga3d9872aeff6bb7b117c36ea4410df912"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3d9872aeff6bb7b117c36ea4410df912">&#9670;&nbsp;</a></span>CY_DMAC_INTR_SRC_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_SRC_BUS_ERROR&#160;&#160;&#160;(DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 1: Bus error for a load from the source. </p>

</div>
</div>
<a id="ga92e5404a2d5c9d5062641bd421c84829"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga92e5404a2d5c9d5062641bd421c84829">&#9670;&nbsp;</a></span>CY_DMAC_INTR_DST_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_DST_BUS_ERROR&#160;&#160;&#160;(DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 2: Bus error for a store to the destination. </p>

</div>
</div>
<a id="gacfac4a721243f6224de04c57fbeaaf6a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gacfac4a721243f6224de04c57fbeaaf6a">&#9670;&nbsp;</a></span>CY_DMAC_INTR_SRC_MISAL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_SRC_MISAL&#160;&#160;&#160;(DMAC_CH_V2_INTR_SRC_MISAL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 3: Misalignment of the source address. </p>

</div>
</div>
<a id="ga8a4463389bb1c3e079456022a30d9c41"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8a4463389bb1c3e079456022a30d9c41">&#9670;&nbsp;</a></span>CY_DMAC_INTR_DST_MISAL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_DST_MISAL&#160;&#160;&#160;(DMAC_CH_V2_INTR_DST_MISAL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 4: Misalignment of the destination address. </p>

</div>
</div>
<a id="ga39b68dc568f3f671eb28d8f52e480538"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga39b68dc568f3f671eb28d8f52e480538">&#9670;&nbsp;</a></span>CY_DMAC_INTR_CURR_PTR_NULL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_CURR_PTR_NULL&#160;&#160;&#160;(DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit 5: The channel is enabled and the current descriptor pointer is "0". </p>

</div>
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<a id="gab33ccbb9279592dcc8bedbf77569ddbb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab33ccbb9279592dcc8bedbf77569ddbb">&#9670;&nbsp;</a></span>CY_DMAC_INTR_ACTIVE_CH_DISABLED</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_DMAC_INTR_ACTIVE_CH_DISABLED&#160;&#160;&#160;(DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk)</td>
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      </table>
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<p>Bit 6: The channel is disabled and the data transfer engine is busy. </p>

</div>
</div>
<a id="gaf018a967f58d71bb541b31690276d835"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf018a967f58d71bb541b31690276d835">&#9670;&nbsp;</a></span>CY_DMAC_INTR_DESCR_BUS_ERROR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define CY_DMAC_INTR_DESCR_BUS_ERROR&#160;&#160;&#160;(DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk)</td>
        </tr>
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<p>Bit 7: Bus error for a load of the descriptor. </p>

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